基于FPGA的数字式竞赛抢答器设计.rar

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摘 要:数字式竞赛抢答器是数字电路中的一个典型性应用。常规的功能有按钮信号输入、优先按键信号锁存、抢答者编号显示、抢答者回答问题时间计时等功能。传统的硬件设计用到的器件较多,连线比较复杂,而且会产生比较大的延迟,从而造成测量误差,使得可靠性变差。随着复杂、可编程逻辑器件CPLD和现场可编程门阵列FPGA的广泛应用,以EDA工具作为开发手段,基于FPGA的数字式竞赛抢答器设计,可以使整个系统大大简化,从而提高了了设计系统的性能和可靠性。本设计给出了数字式竞赛抢答器的设计输入、功能仿真和时序仿真以及硬件测试的全过程。该设计具有较好的移植性和实用性。本系统的设计就是采用VHDL硬件描述语言编程,基于Quartus II平台进行编译和仿真来实现的,其采用的模块化、逐步细化的设计方法有利于系统的分工合作,并且能够及早发现各子模块及系统中的错误,提高系统设计的效率。本设计主要的功能是:1:对第一抢答信号的鉴别和锁存功能2:记分功能3:数码显示功能。

关键词:抢答器;VHDL;仿真

 

Abstract:Digital competition responder is a typical application in digital circuit. The conventional functional is button signal input, priority key signal latch, responder ID display, answering question for timing and it has other functions. The traditional hardware design uses many devices and the connection is more complicated, furthermore, it will produce large delay, so the result is that it will cause the measurement error and make the reliability become bad.  Along with the complex programmable logic device CPLD, and a field programmable gate array FPGA being widely used, based on the FPGA digital competition responder design with the development of EDA tools can greatly simplify the system as a whole, so it can improve the performance and reliability of design the system. The design gives the design of Digital competition responder input, function simulation and timing simulation and hardware test of the whole process. The design has a better portability and usability. This system's design programmed in the VHDL, compiled and emulated basing on Quartus II platform of Altera. Using the modulation, and the gradually detailing design method is of great benefit for the system's division of labor and cooperation, besides, the usage of this method can detect errors, as early as possible , in various of sub modules and system, enhancing the efficiency of the system design. The main feature of this design are: 1. accurately identificating of the signal of the first answer and latching this signal; 2. score function 3. digital display function.

Key words: Responder; VHDL; simulation

 

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